1. Field of the Invention
The present invention relates to a semiconductor apparatus and an anomaly detection method of the same, and, particularly, to a semiconductor apparatus including an arithmetic circuit to execute a program and an anomaly detection method of the same.
2. Description of Related Art
A semiconductor apparatus such as a microcomputer operates based on an operating clock signal that is generated externally. The operating clock signal to be supplied to the microcomputer may be switched for the purpose of reducing the power consumption of a system including the microcomputer or improving the reliability of the microcomputer.
One example of switching the operating clock signal is disclosed in Japanese Unexamined Patent Application Publication No. 4-365110. FIG. 5 is a block diagram showing a semiconductor apparatus 100 disclosed in Japanese Unexamined Patent Application Publication No. 4-365110. The semiconductor apparatus 100 is a clock stop circuit. The semiconductor apparatus 100 includes a clock stop detector 101, a set-reset flip-flop 102, a free-running multivibrator 103, a counter 104, and a selector 105. In the semiconductor apparatus 100, the presence or absence of an external clock signal CKE is detected by the clock stop detector 101. If the stopped state of the external clock signal CKE is detected by the clock stop detector 101, an internal clock signal CKI that is generated by an internal clock generator composed of the set-reset flip-flop 102 and the free-running multivibrator 103 is output as a clock signal CLK to an internal circuit such as a microcomputer during a prescribed period set by the counter 104. The selector 105 selects which of the external clock signal CKE and the internal clock signal CKI is output as the clock signal CLK.
Specifically, in the case where the oscillation of the external clock signal CKE is stopped in order to reduce the power consumption of the system, the semiconductor apparatus 100 operates using the internal clock generator during a prescribed period from the stop of the external clock signal CKE. Therefore, even when the external clock signal CKE is stopped irrespectively of the operation of the microcomputer, the microcomputer can be shifted to the stopped state safely by the internal clock signal CKI in the semiconductor apparatus 100. The semiconductor apparatus 100 thus allows the external clock signal CKE to be stopped irrespectively of the operation of the microcomputer in the case of stopping the external clock signal CKE in order to reduce the power consumption of the system including the microcomputer.
Another example of switching the operating clock signal is disclosed in Japanese Unexamined Patent Application Publication No. 2004-334794. FIG. 6 is a block diagram showing a semiconductor apparatus 200 disclosed in Japanese Unexamined Patent Application Publication No. 2004-334794. The semiconductor apparatus 200 is a phase-locked loop (PLL) and an oscillation stop detector in a microcomputer with a built-in PLL. The semiconductor apparatus 200 further includes an externally generated clock stop circuit to receive an externally generated clock in the previous stage of the PLL and the oscillation stop detector, although not shown in FIG. 6.
Referring to FIG. 6, the semiconductor apparatus 200 includes a PLL 210 and an oscillation stop detector 201. The oscillation stop detector 201 includes an edge detector 220, a 2-bit counter 230, an OR circuit 240, and an externally generated clock signal stop detector 250. If an externally generated clock signal is supplied, the PLL 210 outputs an internal clock signal SCLK having a frequency of n-times multiplication of the externally generated clock signal. If, on the other hand, a low level voltage (e.g. a ground voltage), not an externally generated clock signal, is supplied, the PLL 210 outputs an internal clock signal SCLK having a prescribed frequency. The edge detector 220 detects the edge of the externally generated clock signal. The 2-bit counter 230 is cleared by an output of the edge detector 220 and performs count operation using the internal clock signal as a count source. A clear signal to the 2-bit counter 230 is input through the OR circuit 240. An initialization signal INITIAL and an output signal of the edge detector 220 are input to the OR circuit 240. Thus, the clear signal to the 2-bit counter 230 is a result of a logical OR operation between the initialization signal INITIAL and the output signal of the edge detector 220. If an output of the 2-bit counter 230 exceeds a prescribed set value, the externally generated clock signal stop detector 250 detects it as the stop of the externally generated clock signal and keeps outputting an external clock stop detection signal CT11. Then, if the externally generated clock stop circuit receives the external clock stop detection signal CT11, it blocks the externally generated clock signal and outputs a low level signal.
In this manner, in the semiconductor apparatus 200, when an externally generated clock signal is stopped due to a defect such as a break, the stop of the externally generated clock signal is detected by the oscillation stop detector 201, and the internal clock signal SCLK generated by the PLL 210 is used as an operating clock signal after that. It is thereby possible for the semiconductor apparatus 200 to maintain the operation of the microcomputer or the like even if the stop of the externally generated clock signal occurs due to a break or the like. Therefore, the semiconductor apparatus 200 can ensure high reliability against a defect in the externally generated clock signal.